The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor non-volatile memory.
As a semiconductor non-volatile memory, it has been proposed to adopt a sidewall type (sidewall type memory), in which electron charge accumulation portions with a sidewall shape are disposed on both sides of a gate electrode of one single transistor (refer to Patent Reference).
Patent Reference Japanese Patent Publication No. 2005-64295
With reference to FIG. 6, a conventional semiconductor non-volatile memory will be explained. FIG. 6 is a schematic sectional view showing a conventional semiconductor non-volatile memory 110 of the sidewall type.
In the conventional semiconductor non-volatile memory 110 described in Patent Reference, a memory cell portion 123 for storing information and a peripheral circuit portion 126 for writing and retrieving information to and from the memory cell portion 123 are disposed on a common semiconductor substrate. In general, the memory cell portion 123 and the peripheral circuit portion 126 are provided with a plurality of transistors. In FIG. 6, the memory cell portion 123 and the peripheral circuit portion 126 are provided with one transistor as an example.
The memory cell portion 123 is provided with a first MOS type transistor (first MOSFET or Metal Oxide Semiconductor Field Effect Transistor) 130 disposed on a p-type silicon substrate 120. The first MOSFET 130 is provided with a gate electrode 134, a pair of impurity diffused areas 140a and 140b, and variable resistor portions 142.
The gate electrode 134 is disposed on the silicon substrate 120 through a gate insulation film 132. The impurity diffused areas 140a and 140b are formed through diffusing an n-type impurity in areas of the silicon substrate 120 sandwiching the gate electrode 134. The impurity diffused areas 140a and 140b function as a source and a drain of the first MOSFET 130, respectively.
In the conventional semiconductor non-volatile memory 110 shown in FIG. 6, the impurity diffused area 140a functions and is referred to as a source 140a, and the impurity diffused area 140b functions and is referred to as a drain 140b. 
The variable resistor portions 142 are formed in the silicon substrate 120 between a portion below the gate electrode 134 and the impurity diffused areas 140a and 140b. The variable resistor portions 142 are formed through diffusing the n-type impurity same as that of the impurity diffused areas 140a and 140b at a concentration lower than that of the impurity diffused areas 140a and 140b. 
In the first MOSFET 130 of the memory cell portion 123, charge accumulation portions 150a and 150b are disposed on the variable resistor portions 142. The charge accumulation portions 150a and 150b are formed of a laminated structure of a bottom oxide film 152, a charge accumulation film 154, and a top oxide film 156 sequentially laminated in this order. The charge accumulation portions 150a and 150b are capable of accumulating charges.
In the conventional semiconductor non-volatile memory 110 of the sidewall type, resistivity of the variable resistor portions 142 formed in the silicon substrate 120 below the charge accumulation portions 150a and 150b changes according to whether the charge accumulation portion 150a on a side of the drain 140a and the charge accumulation portion 150b on a side of the source 140b accumulate electrons. A state that the charge accumulation portions 150a and 150b accumulate electrons is designated as 1, and a state that the charge accumulation portions 150a and 150b do accumulate electrons is designated as 0, so that data can be distinguished.
In order to charge electrons into the charge accumulation portion 150a on the side of the drain 140a, the source 140b and the silicon substrate 120 are grounded, and a positive potential is applied to the gate electrode 134 and the drain 140a. At this time, electrons flowing through a channel become a high energy state, i.e., hot electrons, near the drain 140a due to a strong electric field toward the drain 140a. The hot electrons are charged into the charge accumulation portion 150a on the side of the drain 140a due to an electric field toward the gate electrode 134.
In order to retrieve information from the charge accumulation portion 150a on the side of the drain 140a, the drain 140a and the silicon substrate 120 are grounded, and a positive potential is applied to the gate electrode 134 and the source 140b. 
When electrons are accumulated in the charge accumulation portion 150a on the side of the drain 140a, the electrons accumulated in the charge accumulation portion 150a induce positive charges in the variable resistor portion 142 situated below the charge accumulation portion 150a. Accordingly, due to the induced positive charges, the resistivity of the variable resistor portion 142 situated below the charge accumulation portion 150a increases, thereby decreasing a current between the source and the drain (channel current).
On the other hand, when the electrons are not accumulated in the charge accumulation portion 150a on the side of the drain 140a, the resistivity of the variable resistor portion 142 situated below the charge accumulation portion 150a does not change, thereby causing no change in the channel current. Accordingly, through a level of the channel current, it is possible to distinguish whether the charges are accumulated, or the data is 0 and 1.
When one MOSFET having a charge accumulation portion is regarded as a memory unit, i.e., a memory cell, in the memory of the sidewall type, it is possible to store information of two bits in one memory cell through changing a voltage applied to a source and a drain thereof. In the peripheral circuit portion 126, the transistor has a configuration similar to that of the memory cell portion 123 for writing and retrieving information to and from the memory cell portion 123.
The peripheral circuit portion 126 is provided with a second MOSFET 160 disposed on the p-type silicon substrate 120. The second MOSFET 160 is provided with a gate electrode 164, a pair of impurity diffused areas 170, and variable resistor portions 172. The gate electrode 164 is disposed on the silicon substrate 120 through a gate insulation film 162.
In the second MOSFET 160 of the peripheral circuit portion 126, charge accumulation portions 180 are disposed on the variable resistor portions 172. The charge accumulation portions 180 are formed of a laminated structure of a bottom oxide film 182, a charge accumulation film 184, and a top oxide film 186 sequentially laminated in this order. The charge accumulation portions 180 are capable of accumulating charges.
It is possible to concurrently produce the first MOSFET 130 of the memory cell portion 123 and the second MOSFET 160 of the peripheral circuit portion 126. In this case, the first MOSFET 130 and the second MOSFET 160 have an identical configuration.
As described above, in the conventional semiconductor non-volatile memory, similar to the memory cell portion, the peripheral circuit portion has the laminated structure capable of accumulating charges. Accordingly, when the transistor of the peripheral circuit portion is turned on, electrons flowing through the channel become a high-energy state, i.e., hot electrons, near the drain due to a strong electric field toward the drain. The hot electrons are charged into the charge accumulation portion.
When electrons flow through the channel, the electrons may become impact ions due to the strong electric field near the drain. As a result, the impact ions impede with surrounding atoms, thereby generating electron positive hole pairs. When the electrons and the positive holes are accumulated in the charge accumulation portion, a phenomenon called drain avalanche charging may occur.
In the peripheral circuit portion, the charges charged into the charge accumulation portion remain as is. Accordingly, when the field effect transistor is in a turned on state, an amount of the current between the drain and the source may decrease. As a result, in the field effect transistor with the peripheral circuit portion, as compared with normal deterioration due to charging and trapping electrons or positive holes in the gate insulation film, the charges thus remaining have a large influence on the change in the amount of the current, thereby lowering reliability of the element.
In view of the problems described above, an object of the present invention is to provide a semiconductor device to solve the problems of the conventional semiconductor device, and a method of producing the semiconductor device. In particular, in the semiconductor of the invention, it is arranged to reduce an amount of charges, i.e., hot carriers, charged into a charge accumulation film in a peripheral circuit portion. Accordingly, it is possible to effectively prevent the peripheral circuit portion from deteriorating due to the hot carriers.
Further objects and advantages of the invention will be apparent from the following description of the invention.